Integrated circuits are often designed to incorporate scan test circuitry that facilitates testing for various internal fault conditions. Such scan test circuitry typically comprises scan chains comprising multiple scan cells. The scan cells may be implemented, by way of example, utilizing respective flip-flops. The scan cells of a given scan chain are configurable to form a serial shift register for applying test patterns at inputs to combinational logic of the integrated circuit. The scan cells of the given scan chain are also used to capture outputs from other combinational logic of the integrated circuit.
Scan testing of an integrated circuit may therefore be viewed as being performed in two repeating phases, namely, a scan shift phase in which the flip-flops of the scan chain are configured as a serial shift register for shifting in and shifting out of respective input and output scan data, and a scan capture phase in which the flip-flops of the scan chain capture scan data from combinational logic. These two repeating scan test phases are often collectively referred to as a scan test mode of operation of the integrated circuit.
Outside of the scan test mode and its scan shift and capture phases, the integrated circuit may be said to be in a functional mode of operation. Other definitions of the scan test and functional operating modes may also be used. For example, the capture phase associated with a given scan test may instead be considered part of a functional mode of operation, such that the modes include a scan shift mode having only the scan shift phase, and a functional mode that includes the capture phase.
In scan testing of an integrated circuit, capture of non-deterministic values from circuitry under test can lead to significant problems. This is particularly true for integrated circuits that include multiplexers having specified constraints on their select signal inputs, such as so-called “one-hot” multiplexers in which only one of multiple select signal inputs of the multiplexer can be at a logic high signal level at any particular time. Such one-hot multiplexers are commonly used to achieve faster circuit operation in high-speed applications. In order to avoid damaging or otherwise degrading this important functionality of the multiplexer, the select signal constraint of the multiplexer should be satisfied when testing the integrated circuit, including both during external testing using automated test equipment (ATE) as well as during on-chip self-testing using logic built-in self-test (LBIST) circuitry. These and other types of testing commonly involve use of scan test circuitry of the type previously described. However, conventional scan test circuitry is often unable to provide adequate assurances that multiplexer select signal constraints will be satisfied during scan testing of the integrated circuit.